Flash memory is a type of memory that is non-volatile, can be electrically erased and written, and that offers short read access times. For these reasons, flash memory has become increasingly popular in portable devices such as smartphones, digital music players, and the like, as well as in computer systems in the form of solid-state drives. Flash memory is generally implemented in a manner similar to that of NAND logic gates, and so is often referred to as NAND flash memory.
Manufacturers are currently producing many kinds of NAND flash memory, each with different modes, speeds, and protocols. These modes, speeds, and protocols are constantly evolving. In addition, some manufacturers are implementing proprietary features. Furthermore, some NAND flash memories are capable of operations in multiple protocols such as single data rate and double data rate protocols. It is difficult for customers to keep pace with these developments as they integrate these memories into their systems.
FIG. 1 shows a conventional non-volatile memory system 100. Non-volatile memory system 100 includes a non-volatile memory 110, a non-volatile memory controller 108, and a processor 106. Non-volatile memory controller 108 includes a single data rate (SDR) state machine 122A, a double data rate (DDR) state machine 122B, and a non-volatile memory interface 124. To program non-volatile memory 110, processor 106 provides SDR commands 130A to SDR state machine 122A, and provides DDR commands 130B to DDR state machine 122B. In response, SDR state machine 122A generates pad signals 126A, and DDR state machine 122B generates pad signals 126B. Non-volatile memory interface 124 provides the pad signals 126 to pads 128 of non-volatile memory 110.
In a conventional non-volatile memory system 100, changes to the modes, speeds, protocols, and the like for non-volatile memory 110 are accommodated by changing the design of the state machines 122 in the non-volatile memory controller 108. However, such changes are expensive and time-consuming to implement. In addition, changing protocols during operation requires switching from one state machine 122 to the other, after waiting for all operations of the first state machine to finish. For example, when changing from SDR protocol to DDR protocol, the non-volatile memory controller 108 must wait until all operations of the SDR state machine 122A have completed before starting the DDR state machine 122B. This costs considerable time.